Evaluating Codee’s Impact on SiFive’s LLVM RISC-V Development Ecosystem

The RISC-V instruction set architecture (ISA) is an open-source, customizable foundation for processors, gaining traction in industries like Embedded Systems, Edge Computing, AI/ML, High-Performance Computing (HPC), Storage and Networking, Automotive, Aerospace and Defense. However, it faces competition from established architectures like ARM and x86, which have mature software ecosystems. Thus, building a robust ecosystem of software tools, libraries, and developer support is crucial for the success of RISC-V.

Codee is the first static code analyzer specialized in performance, designed to be a complement, not a replacement, for the compiler, profiler, debugger and IDE. Codee helps write compiler-friendly and hardware friendly code, favoring maintainability and readability. It has demonstrated up to 18x performance boosts in HPC workloads with Intel Xeon processors.

This post explores the potential impact of Codee on the RISC-V ecosystem, particularly with SiFive’s LLVM-based tools and the P470 processor.

The study is the first to use Codee with LLVM and RISC-V presented at the RISC-V Summit Europe 2024. Results show Codee can boost performance by up to 7x on SiFive’s P470 processors with the latest LLVM/Clang compiler at maximum optimization. Codee enhances vectorization efficiency by identifying and optimizing loops better than the compiler alone. We believe Codee significantly improves the LLVM+RISC-V ecosystem, helping developers create high-performance code in terms of speed, size, and energy efficiency. 

Experimental Results

Experiments were conducted on a machine using SiFive LLVM-Linux 15.9.0-2023.03.0, with clang version 15.9.0 targeting SiFive’s RISC-V P470 processor. The P470 processor ran at 32MHz on a Xilinx VCU118 Ultrascale FPGA. Performance was measured as the average of five runs, using compiler optimization flags -O3 -ffast-math. Codee version 2023.1.6 optimized the source code before compilation.

Both Codee’s detection capabilities and AutoFix’es were utilized, focusing on single-core optimizations, particularly vectorization efficiency and sequential memory accesses to avoid cache misses.

MATMUL Benchmark

• Various implementations from the Open Catalog of Code Guidelines for Correctness, Modernization, and Optimization were evaluated.
• Codes ran 1.5x to 7.5x faster on the P470 processor as shown in the figure below.
• Improvements resulted from applying loop interchange to perfectly nested and non-perfectly nested loops.
• PWR039 enables the vectorization of a loop missed by SiFive LLVM/Clang.
• PWR043 and PWR062 increase the efficiency of loops vectorized by SiFive LLVM/Clang by favoring sequential memory accesses that avoid cache misses.

Performance boost of MATMUL on SiFive’s RISC-V P470 processor.

MBedTLS Benchmark

• Evaluated cryptographic algorithms.
• Codee improved performance by over 34% on the SiFive P470 processor for the codes MD5, SHA-256 and 3DES.
• Gains were due to higher vectorization efficiency.

 Performance boost of MBedTLS on SiFive’s RISC-V P470 processor.

Conclusions

The results on SiFive’s P470 processor reveal that Codee brings a new and revolutionary solution that makes the upstream LLVM+RISC-V ecosystem even better, helping developers to deliver code with high performance in terms of speed, size and energy consumption.